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| Semiconductor NOT October 1998 N FOR DED 5805 N MME ee HI S ECO R E ES WD IGN S HI5804 12-Bit, 5 MSPS A/D Converter Features * Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MSPS * Low Power * Internal Sample and Hold * Fully Differential Architecture * Full Power Input Bandwidth . . . . . . . . . . . . . . . 100MHz Description The HI5804 is a monolithic, 12-bit, Analog-to-Digital Converter fabricated in Harris' HBC10 BiCMOS process. It is designed for high speed, high resolution applications where wide bandwidth and low power consumption are essential. The HI5804 is designed in a fully differential pipelined architecture with a front end differential-in-differential-out sample-and-hold (S/H). The HI5804 has excellent dynamic performance while consuming 300mW power at 5 MSPS. [ /Title (HI5804) * Low Distortion /Subject (12-Bit, 5 MSPS A/D Converter) The 100MHz full power input bandwidth is ideal for * Internal() /Author Reference communication systems and document scanner * TTL/CMOS(Harris Semiconductor, A/D, Analog to Dig/Keywords Compatible Digital I/O applications. Data output latches are provided which present ital Converter, Narrow Band, . . . . . . . . . . . . 3V to High * Digital Outputs . . . . . . . . . . . . . .Communications, 5V valid data to the output bus with a latency of 3 clock cycles. The Speed Converters, High Resolution Converters, Basesta-digital outputs have a separate supply pin which can be powered from a 3.0V to 5.0V supply. Applications tion, Cellular) /Creator () Data Acquisition Systems Ordering Information * High Speed /DOCINFO pdfmark * Digital IF Communication Systems * Document and Film Scanners PART NUMBER SAMPLE RATE 5 MSPS TEMP. RANGE (oC) 0 to 70 25 PACKAGE 28 Ld SOIC PKG. NO. [ /PageMode /UseOutlines * Medical Imaging /DOCVIEW pdfmark * Radar Signal Analysis HI5804KCB HI5804EVAL M28.3 Evaluation Board * Vibration/Waveform Spectrum Analysis * Digital Servo Loop Control * Reference Literature - AN9214 Using Harris High Speed Converters - AN9647 Using the HI5804 Evaluation Board Pinout HI5804 (SOIC) TOP VIEW CLK 1 DVCC1 2 DGND1 3 DVCC1 4 DGND1 5 AVCC 6 28 D0 27 D1 26 D2 25 D3 24 D4 23 D5 22 DVCC2 AGND 7 VIN+ 8 VIN- 9 VDC 10 VROUT 11 VRIN 12 AGND 13 AVCC 14 21 DGND2 20 D6 19 D7 18 D8 17 D9 16 D10 15 D11 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1998 File Number 4026.5 1 HI5804 Functional Block Diagram VDC VINVIN+ S/H STAGE 1 DVCC2 BIAS CLOCK REF CLK VROUT VRIN 4-BIT FLASH + X8 4-BIT DAC - D11 (MSB) D10 DIGITAL DELAY AND DIGITAL ERROR CORRECTION D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) STAGE 3 4-BIT FLASH + X8 4-BIT DAC - STAGE 4 4-BIT FLASH DGND2 AVCC AGND DVCC1 DGND1 Typical Application Schematic (LSB) (28) D0 (27) D1 (26) D2 VROUT (11) (25) D3 VRIN (12) (24) D4 AGND (7) (23) D5 AGND (13) (20) D6 DGND1 (3) (19) D7 DGND1 (5) (18) D8 DGND2 (21) (17) D9 (16) D10 (MSB) (15) D11 VIN+ VIN+ (8) VDC (10) VINCLOCK VIN- (9) CLK (1) (4) DVCC1 (2) DVCC1 (22) DVCC2 0.1F (6) AVCC (14) AVCC HI5804 0.1F + 10F + 10F D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DGND AGND BNC 2 HI5804 Absolute Maximum Ratings Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . . +6.0V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC Thermal Information Thermal Resistance (Typical, Note 1) JA(oC/W) HI5804KCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, HI5804KCB . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVCC = DVCC1 = DVCC2 = +5.0V, fS = 5 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF, TA = 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate Effective Number of Bits, ENOB Signal to Noise and Distortion Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal = -----------------------------RMS Noise Total Harmonic Distortion, THD 2nd Harmonic Distortion 3rd Harmonic Distortion Spurious Free Dynamic Range, SFDR Intermodulation Distortion, IMD Transient Response Over-Voltage Recovery ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (VIN+ - VIN-) Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB+ or IBDifferential Analog Input Bias Current IB DIFF = (IB+ - IB-) Full Power Input Bandwidth, FPBW Analog Input Common Mode Voltage (VIN+ + VIN-)/2 12 fIN = DC fIN = DC fIN = DC fIN = DC No Missing Codes No Missing Codes fIN = 1MHz fIN = 1MHz - 2 0.5 12 24 1 - Bits LSB LSB LSB LSB - 0.5 5 10.3 64 - MSPS MSPS Bits dB fIN = 1MHz - 65 - dB fIN = 1MHz fIN = 1MHz fIN = 1MHz fIN = 1MHz f1 = 1MHz, f2 = 1.02MHz 0.2V Overdrive - -70 -73 -73 73 -66 1 2 2.0 4.0 10 0.5 100 2.3 - dBc dBc - dBc dBc dBc Cycle Cycle (Notes 2, 3) 1 -10 Differential Mode (Note 2) 1 - V V M pF A A MHz V +10 - 4 3 HI5804 Electrical Specifications AVCC = DVCC1 = DVCC2 = +5.0V, fS = 5 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF, TA = 25oC, Unless Otherwise Specified (Continued) TEST CONDITIONS MIN TYP MAX UNITS PARAMETER INTERNAL VOLTAGE REFERENCE Reference Output Voltage, VROUT Reference Output Current REFERENCE INPUT Total Reference Resistance, RL Reference Current DC BIAS VOLTAGE DC Bias Voltage Output, VDC Max Output Current (Not to Exceed) DIGITAL INPUT, CLK Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS, D0-D11 Output Logic Sink Current, IOL Output Logic Source Current, IOH Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Delay, tOD Data Output Hold, t H Data Latency, tLAT Clock Pulse Width (Low) Clock Pulse width (High) POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVCC Digital Supply Voltage, DVCC1 Digital Output Supply Voltage, DVCC2 Total Supply Current, ICC Analog Supply Current, AICC Digital Supply Current, DICC1 Digital Output Supply Current, DICC2 Power Dissipation Offset Error Sensitivity, VOS Gain Error Sensitivity, FSE NOTES: - 3.5 - 1 V mA - 7.8 450 - k A - 2.3 - 1 V mA 2.0 VCLK = 5V VCLK = 0V - 7 0.8 10.0 10.0 - V V A A pF VO = 0.4V (Note 2) DVCC2 = 3.0V, VO = 0.4V VO = 2.4V (Note 2) DVCC2 = 3.0V, VO = 2.4V 1.6 -0.2 - 1.6 -0.2 5 - mA mA mA mA pF For a Valid Sample (Note 2) 5MHz Clock 5MHz Clock 90 90 5 5 8 8 100 100 3 110 110 ns psRMS ns ns Cycle ns ns 4.75 4.75 2.85 VIN+ - VIN- = 2V VIN+ - VIN- = 2V VIN+ - VIN- = 2V VIN+ - VIN- = 2V VIN+ - VIN- = 2V AVCC or DVCC = 5V 5% AVCC or DVCC = 5V 5% - 5.0 5.0 60 46 13 1 300 16 16 5.25 5.25 5.25 - V V V mA mA mA mA mW LSB LSB 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock off (clock low, hold mode). 4 HI5804 Timing Waveforms ANALOG INPUT CLOCK INPUT SN - 1 HN - 1 SN HN SN + 1 HN + 1 SN + 2 HN + 2 SN + 3 HN + 3 SN + 4 HN + 4 SN+5 HN + 5 SN + 6 HN + 6 INPUT S/H 1ST STAGE B1, N - 1 B1, N B1, N + 1 B1, N + 2 B1, N + 3 B1, N + 4 B1, N + 5 2ND STAGE B2, N - 2 B2, N - 1 B2, N B2, N + 1 B2, N + 2 B2, N + 3 B2, N + 4 3RD STAGE 4TH STAGE B3, N - 2 B3, N - 1 B3, N B3, N + 1 B3, N + 2 B3, N + 3 B3, N + 4 B4, N - 3 B4, N - 2 B4, N - 1 B4, N B4, N + 1 B4, N + 2 B4, N + 3 DATA OUTPUT DN - 3 DN - 2 tLAT DN - 1 DN DN + 1 DN + 2 DN + 3 NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM , N : M-th stage digital output corresponding to N-th sampled input.DN : Final data output corresponding to N-th sampled input. FIGURE 1. HI5804 INTERNAL CIRCUIT TIMING ANALOG INPUT t AP t AJ CLOCK INPUT 1.5V 1.5V tOD tH 2.0V DATA N-1 0.8V DATA N DATA OUTPUT FIGURE 2. INPUT-TO-OUTPUT TIMING 5 HI5804 Typical Performance Curves 11.0 EFFECTIVE NUMBER OF BITS (ENOB) fS = 5 MSPS 10.8 70oC 10.6 25oC SINAD (dB) 65 66 70oC 25oC 67 fS = 5 MSPS 10.4 64 10.2 63 10.0 1 2 3 4 INPUT FREQUENCY (MHz) 5 62 1 2 3 4 INPUT FREQUENCY (MHz) 5 FIGURE 3. TYPICAL ENOB vs INPUT FREQUENCY FIGURE 4. TYPICAL SINAD vs INPUT FREQUENCY 68 fS = 5 MSPS 67 78 fS = 5 MSPS 77 25oC 66 SNR (dB) 70oC 65 64 63 62 1 2 -THD (dBc) 25oC 76 70oC 75 74 73 72 3 4 INPUT FREQUENCY (MHz) 5 1 2 3 4 INPUT FREQUENCY (MHz) 5 FIGURE 5. TYPICAL SNR vs INPUT FREQUENCY FIGURE 6. TYPICAL -THD vs INPUT FREQUENCY 80 25oC 70oC 78 SFDR (dBc) fS = 5 MSPS POWER DISSIPATION (mW) 340 fS = 5 MSPS VIN+ = VIN- = VDC 320 300 76 70oC 74 25oC 280 260 72 1 2 3 4 INPUT FREQUENCY (MHz) 5 240 15 25 35 45 55 65 75 TEMPERATURE (oC) FIGURE 7. TYPICAL SFDR vs INPUT FREQUENCY FIGURE 8. TYPICAL POWER DISSIPATION vs TEMPERATURE 6 HI5804 Pin Descriptions PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME CLK DVCC1 DGND1 DVCC1 DGND1 AVCC AGND VIN+ VINVDC VROUT VRIN AGND AVCC D11 D10 D9 D8 D7 D6 DGND2 DVCC2 D5 D4 D3 D2 D1 D0 DESCRIPTION Sample Clock Input. Digital Supply (+5.0V). Digital Ground. Digital Supply (+5.0V). Digital Ground. Analog Supply (+5.0V). Analog Ground. Positive Analog Input. Negative Analog Input. DC Bias Voltage Output. Reference Voltage Output. Reference Voltage Input. Analog Ground. VIN VIN + clock which is a non-overlapping two phase signal, 1 and 2 , derived from the master clock. During the sampling phase, 1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of 1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-and-hold function but will also convert a single-ended input to a fully-differential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 100MHz for the converter. 1 1 2 1 CS CS + CH 1 -+ CH VOUT + VOUT - Analog Supply (+5.0V). Data Bit 11 Output (MSB). Data Bit 10 Output. Data Bit 9 Output. Data Bit 8 Output. Data Bit 7 Output. Data Bit 6 Output. Digital Output Ground. Digital Output Supply (+3.0V to +5.0V). Data Bit 5 Output. Data Bit 4 Output. Data Bit 3 Output. Data Bit 2 Output. Data Bit 1 Output. Data Bit 0 Output (LSB). 1 1 FIGURE 9. ANALOG INPUT SAMPLE-AND-HOLD As illustrated in the functional block diagram and the timing diagram in Figure 1, three identical pipeline subconverter stages, each containing a four-bit flash converter, a four-bit digital-to-analog converter and an amplifier with a voltage gain of 8, follow the S/H circuit with the fourth stage being only a four bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual sub-converter clock signal is offset by 180 degrees from the previous stage clock signal with the result that alternate stages in the pipeline will perform the same operation. The 4-bit digital output of each stage is fed to a digital delay line controlled by the internal clock. The purpose of the delay line is to align the digital output data to the corresponding sampled analog input signal. This delayed data is fed to the digital error correction circuit which corrects the error in the output data with the information contained in the redundant bits to form the final twelve bit output for the converter. Because of the pipeline nature of this converter, the data on the bus is output at the 3rd cycle of the clock after the analog sample is taken. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The output data is synchronized to the external clock by a latch. The digital outputs are in offset binary format (See Table 1). Detailed Description Theory of Operation The HI5804 is a 12-bit, fully-differential, sampling pipeline A/D converter with digital error correction. Figure 9 depicts the circuit for the front end differential-in-differential-out sample-and-hold (S/H). The switches are controlled by an internal 7 HI5804 Internal Reference Generator, VROUT and VRIN The HI5804 has an internal reference voltage generator, therefore no external reference voltage is required. VROUT must be connected to VRIN when using the internal reference voltage. The HI5804 can be used with an external reference voltage. The converter requires only one external reference voltage connected to the VRIN pin with VROUT left open. The HI5804 is tested with VRIN equal to 3.5V. Internal to the converter two reference voltages of 1.3V and 3.3V are generated for a fully differential input signal range of 2V. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VRIN . Analog Input, Differential Connection The analog input to the HI5804 can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 10) will give the best performance for the converter. VIN VIN+ VDC HI5804 VIN- FIGURE 11. AC COUPLED SINGLE ENDED INPUT Again, the difference between the two internal voltage references is 2V. If VIN is a 4VP-P sinewave, then VIN+ is a 4VP-P sinewave riding on a positive voltage equal to VDC. The converter will be at positive full scale when VIN+ is at VDC + 2V (VIN+ - VIN- = 2V) and will be at negative full scale when VIN+ is equal to VDC - 2V (VIN+ - VIN- = -2V). In this case, VDC could range between 2V and 3V without a significant change in ADC performance. The simplest way to produce VDC is to use the VDC bias voltage output of the HI5804. A single ended source will give better overall system performance if it is first converted to differential before driving the analog input of the HI5804. Digital I/O and Clock Requirements The HI5804 provides a standard high-speed interface to external TTL/CMOS logic families. The digital CMOS clock input has TTL level thresholds. The low input bias current allows the HI5804 to be driven by CMOS logic. The digital CMOS outputs have a separate digital supply. This allows the digital outputs to operate from a 3.0V to 5.0V supply. When driving CMOS logic, the digital outputs will swing to the rails. When driving standard TTL loads, the digital outputs will meet standard TTL level requirements even with a 3.0V supply. In order to ensure rated performance of the HI5804, the duty cycle of the clock should be held at 50% 5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5804 will only be guaranteed at conversion rates above 0.5 MSPS. This ensures proper performance of the internal dynamic circuits. Supply and Ground Considerations The HI5804 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5804 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. Refer to Application Note AN9214, "Using Harris High Speed A/D Converters" for additional considerations when using high speed converters. VIN VIN+ HI5804 VDC -VIN VIN- FIGURE 10. AC COUPLED DIFFERENTIAL INPUT Since the HI5804 is powered off a single +5V supply, the analog input must be biased so it lies within the analog input common mode voltage range of 1.0V to 4.0V. The performance of the ADC does not change significantly with the value of the common mode voltage. A 2.3V DC bias voltage source, VDC , half way between the top and bottom internal reference voltages, is made available to the user to help simplify circuit design when using a differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the analog input common mode voltage range over temperature. The difference between the converter's two internal voltage references is 2V. For the AC coupled differential input, (Figure 10), if VIN is a 2VP-P sinewave with -VIN being 180 degrees out of phase with VIN, the converter will be at positive full scale when the VIN+ input is at VDC + 1V and the VINinput is at VDC - 1V (VIN+ - VIN- = 2V). Conversely, the ADC will be at negative full scale when the VIN+ input is equal to VDC - 1V and VIN- is at VDC + 1V (VIN+ - VIN- = -2V). Analog Input, Single-Ended Connection The configuration shown in Figure 11 may be used with a single ended AC coupled input. Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND. 8 HI5804 TABLE 1. A/D CODE TABLE DIFFERENTIAL INPUT VOLTAGE (USING INTERNAL REFERENCE) +1.99976V OFFSET BINARY OUTPUT CODE MSB D11 1 D10 1 D9 1 D8 1 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 LSB D0 1 CODE CENTER DESCRIPTION +Full Scale (+FS) - 1/4 LSB +FS - 11/4 LSB + 3/4 LSB - 1/4 LSB -FS + 13/4 LSB -Full Scale (-FS) + 3/4 LSB 1.99878V 732.4V -244.1V -1.99829V -1.99927V 1 1 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 1 0 The voltages listed above represent the ideal center of each offset binary output code. Static Performance Definitions Offset Error (VOS) The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. Full-Scale Error (FSE) The last code transition should occur for an analog input that is 3/4 LSB below positive full-scale with the offset error removed. Full-scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Power Supply Sensitivity Each of the power supplies are moved plus and minus 5% and the shift in the offset and gain error (in LSBs) is noted. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Intermodulation Distortion (IMD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present on the inputs. The ratio of the measured distortion terms to the signal is calculated. The terms included in the calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2), (2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each tone 6dB below full scale. where: VCORR = 0.5dB VCORR adjusts the ENOB for the amount the input is below fullscale. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency, excluding DC. Effective Number Of Bits (ENOB) The effective number of bits (ENOB) is calculated from the SINAD data by: ENOB = (SINAD + V CORR - 1.76 )/6.02 Signal-to-Noise Ratio (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5804. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. 9 HI5804 Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component in the spectrum below fS/2. Transient Response Transient response is measured by providing a full scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 12-bit accuracy. Overvoltage Recovery Overvoltage Recovery is measured by providing a full scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 12-bit accuracy. Full Power Input Bandwidth (FPBW) Full power input bandwidth is the frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has a peak-to-peak amplitude equal to the difference between the two internal voltage references. The bandwidth given is measured at the specified sampling frequency. Timing Definitions Refer to Figure 1 and Figure 2 for these definitions. Aperture Delay (tAP) Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter (tAJ) Aperture Jitter is the RMS variation in the aperture delay due to variation of internal clock path delays. Data Hold Time (tH) Data hold time is the time to where the previous data (N - 1) is no longer valid. Data Output Delay Time (tOD) Data output delay time is the time to where the new data (N) is valid. Data Latency (tLAT) After the analog sample is taken, the digital data is output on the bus after the third cycle of the clock. This is due to the pipeline nature of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input sample by 3 clock cycles. 10 HI5804 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 B C D E A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 11 |
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